Semiconductor processing is an increasingly complex and mature technology for which the cost of test and burn-in consumes an ever larger share of production costs. However, continuous progress is being made in semiconductor technology and wafer fabrication efficiency where such progress can be characterized by Moore's law which has successfully predicted a doubling of the number of devices on a semiconductor chip every two years. Productivity gains from advances in semiconductor technology and wafer fabrication efficiency underlie the modern economy, making possible mobile electronics, Internet communications and much of modern life. However, semiconductor packaging and testing have not maintained the same pace of technological progress.
Methods commonly used for contacting individual, separated semiconductor chips during testing have remained largely the same for decades. For example, after wafer probe testing, a wafer is sawn apart into individual chips. Then, additional packaging steps may be used to protect the chip and facilitate its attachment to an electronic system. After packaging, each chip is inserted into a first socket to test for opens and shorts. Each chip is then released from the first socket and transported in a tray. In an optional next step, the chip is inserted into a second (burn-in) socket and burned-in for eight hours at an elevated temperature of about 125° C. After burn-in, the chip is removed from the burn-in socket and transported in a tray to final test where it is inserted into a third socket. A comprehensive set of tests is done in final test, which tests are typically done at several speeds, voltages and temperatures. The socketing, sockets, fixtures, test boards and handling involved with the process of testing individual chips and other microelectronic devices present increasing problems in streamlining the production of semiconductor devices.
Attempts have been made to eliminate the need for individual sockets in test and burn-in, with limited success, in certain segments of the industry. For example, wafer probe testing using full wafer contactors has been used to test and burn-in all chips on a wafer in parallel, simultaneously. In DRAM and FLASH memory production, wafer probe testing is now being done in parallel for each chip on a wafer. However, at present, cost and performance limitations prevent the practical use of full wafer contactors to burn-in and performance test all chips on a wafer. In particular, for more complex chips, such as microprocessors, signal processors, ASICS and communications chips, the high I/O count, power and performance associated with these complex chips prevent use of full wafer contactors for anything other than simple wafer probe testing at best. Although considerable resources, including work in university, U.S. government and industrial laboratories, have been devoted to full wafer burn-in and speed testing, the problem of finding a practical solution remains unsolved.
Other attempts to test and burn-in devices have been made which entail contacting a strip of partially packaged chips. In the process of packaging semiconductor chips as chip scale packages (CSPs) or ball grid arrays (BGAs), an array of chips is held together in a strip format. An array contactor is then used to test and burn-in arrays of chips in the strip format by having the array contactor contact terminals on each partially packaged chip without using an individual chip socket. After testing, the process of packaging the chips is completed, and the strip is sawn into individual finished devices. While testing in a strip format eliminates the need for individual costly sockets for some electrical tests, strip testing is only applicable to packages that are processed in strip format. Dimensional stability limits the application of testing in a strip format to relatively small array sizes and low densities due to problems with alignment of terminals on devices to corresponding contactors. A further limitation results from a complication of the process flow wherein devices leave a packaging area to be tested in a test facility, and then return to packaging for finishing and singulation into individual devices.
Another approach involves placing chips, whether packaged or not, in an accurately positioned array on a carrier. The carrier is moved automatically through the process on tracks or belts. In order to test devices in the carrier, the carrier is physically picked up and placed accurately on the contactor. After testing, the carrier is extracted from the contactor and physically placed back on a track for automatic transport to a next operation. A complex, slow and expensive mechanical apparatus is required to place the carrier accurately on a mating contactor.